Updated 7'' TFT with Cap. Touch for MCVEVP

We are happy to anounce the availability of the updated MxxDK display kit for MCVEVP.

The MxxDK supports a 7" (177.80mm) display with a viewing area of 154.90mm W x 86.85mm H and a capcitive touch, as well. The frame buffer functionality is implemented based on the “VIP Frame Buffer II” IP core by Intel.

More information is available on the respective QuickStart document. Keep us posted in case you want to have it implemented using different display size, resolution, etc.

RISC-V & FreeRTOS for SpiderSoM

RISC-V is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Since its introduction the architecture is gaining more and more popularity in industry.

Please note our updated example for using a RISC V core on SpiderSoM and MX10 under http://www.spiderboard.org. The example shows the setup of the VectorBlox ORCA Core and the RISC-V tools, running FreeRTOS.

 

M100PF - featuring Microsemi PolarFire FPGAs

The M100PF SoM family spans from 100K logic elements (LEs) to 300K LEs, features 12.7G transceivers and offers up to 50% lower power than competing mid-range FPGAs. The devices are ideal for a wide range of applications within wireline access networks and cellular infrastructure, defense and commercial aviation markets, as well as industrial automation and IoT markets.

PolarFire FPGAs offer various device features such as design security, low power devices and data security. All PolarFire FPGAs are integrated with multi-protocol industry-leading low-power transceivers.