RISC-V is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Since its introduction the architecture is gaining more and more popularity in industry.

Please note our updated example for using a RISC V core on SpiderSoM and MX10 under http://www.spiderboard.org. The example shows the setup of the VectorBlox ORCA Core and the RISC-V tools, running FreeRTOS.

We say Thank you ! for dropping by and the interesting conversations we had on the FPGA Kongress.

As we were asked about it: The howto for installling the RISC V softcore on Spiderboard is available on www.spiderboard.org.

The M100PF SoM family spans from 100K logic elements (LEs) to 300K LEs, features 12.7G transceivers and offers up to 50% lower power than competing mid-range FPGAs. The devices are ideal for a wide range of applications within wireline access networks and cellular infrastructure, defense and commercial aviation markets, as well as industrial automation and IoT markets.

PolarFire FPGAs offer various device features such as design security, low power devices and data security. All PolarFire FPGAs are integrated with multi-protocol industry-leading low-power transceivers.

We are looking for talented, enthusiastic hardworking Engineers at all levels with expertise in designing, developing, modifying and evaluating FPGA and SoC FPGA platforms.

Some of the tasks for potential candidates would be

Thanks for a great show with numerous interesting and promising meetings.

We hope you had a safe trip home !

Save the date !

ARIES Embedded launches the new M100PF System-on-Module (SoM) based on Microchip's PolarFire FPGA family at the Embedded World trade fair, taking place in Nuremberg, Germany, from February 26 to 28, 2019.