RISC-V & FreeRTOS for SpiderSoM
RISC-V is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Since its introduction the architecture is gaining more and more popularity in industry.
Please note our updated example for using a RISC V core on SpiderSoM and MX10 under http://www.spiderboard.org. The example shows the setup of the VectorBlox ORCA Core and the RISC-V tools, running FreeRTOS.